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? e91z07h0z-te sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. absolute maximum ratings (ta=25 ?) supply voltage v dd 7v reference voltage v rt , v rb v dd + 0.5 to v ss 0.5 v input voltage v in v dd + 0.5 to v ss ?0.5 v (analog) input voltage v i v dd + 0.5 to v ss ?0.5 v (digital) output voltage v o v dd + 0.5 to v ss ?0.5 v (digital) storage temperature tstg ?5 to +150 ? recommended operating conditions supply voltage av dd , av ss 4.75 to 5.25 v dv dd , dv ss | dv ss ?av ss | 0 to 100 mv reference input voltage v rb 0 and above v v rt 2.7 and below v analog input v in 1.8 vp-p above clock pulse width tpw 1 , tpw 0 13 ns (min) to 1.1 ? (max) operating ambient temperature topr ?0 to +85 ? description the CXD1179Q is an 8-bit cmos a/d converter for video with synchronizing clamp function. the adoption of 2 step-parallel method achieves ultra-low power consumption and a maximum conversion speed of 35msps. features resolution: 8-bit 1/2lsb (dl) maximum sampling frequency: 35msps low power consumption: 80 mw (at 35msps typ.) (reference current excluded) synchronizing clamp function clamp on/off function reference voltage self bias circuit input cmos compatible 3-state ttl compatible output single 5v power supply low input capacitance: 8 pf reference impedance: 330 ? (typ.) applications wide range of applications that require high-speed a/d conversion such as tv and vcr. structure silicon gate cmos ic 8-bit 35msps video a/d converter with clamp function 32 pin qfp (plastic) CXD1179Q
? CXD1179Q block diagram 2 3 4 5 6 7 8 10 11 12 9 30 31 32 1 clock generator upper data latch lower data latch lower encoder (4 bit) lower encoder (4 bit) upper encoder (4 bit) lower sampling comparator (4 bit) lower sampling comparator (4 bit) upper sampling comparator (4 bit) reference supply 26 27 29 28 25 24 23 22 21 20 19 18 17 16 15 14 13 dvss ccp vref cle vrbs vrb avss avss v in av dd av dd vrts av dd clp test (v dd or vss) test (v dd or vss) nc test (open) clk test (dv dd ) dv dd d7 (msb) d6 d5 d4 d3 d2 d1 d0 (lsb) dvss oe vrt
3 CXD1179Q pin description pin no. symbol equivalent circuit description 1 to 8 d0 to d7 test clk test d0 (lsb) to d7 (msb) output leave open during normal usage. clock input fix pin 11 to v dd , pins 13 and 14 to v dd or v ss during normal usage. 9 12 11, 13, 14 di 9 dv dd dv ss 12 dv dd dv ss 11 13 14 dv dd dv ss 10 dv dd digital +5 v
4 CXD1179Q 15 clp 18 vrt 24 vrb 21 v in 25 vrbs 17 vrts inputs clamp pulse to pin 15 (clp). clamps the signal voltage during low interval. generates about +2.6 v when shorted with vrt. reference voltage (top) reference voltage (bottom) analog input generates about +0.6 v when shorted with vrb. pin no. symbol equivalent circuit description 22, 23 av ss 16, 19, 20 av dd 15 dv dd dv ss 17 av dd 18 24 av dd av ss 21 av dd av ss 25 av ss analog +5 v analog ground
5 CXD1179Q pin no. symbol equivalent circuit description 26 vref ccp cle oe clamp reference voltage input. clamps so that the reference voltage and the input signal during clamp interval are equal. integrates the clamp control voltage. the relationship between the changes in ccp voltage and in v in voltage is positive phase. the clamp function is enabled when cle = low. the clamp function is set to off and the converter functions as a normal a/d converter when cle = high. the clamp pulse can be measured by connecting cle to dv dd through a several hundred ? resistor. data is output when oe = low. pins d0 to d7 are at high impedance when oe = high. 27 29 30 26 av dd av ss av dd av ss 27 dv dd dv ss 29 clamp pulse 30 dv dd dv ss 28, 31 dv ss digital ground 32 nc nc pin
6 CXD1179Q digital output the following table shows the relationship between analog input voltage and digital output code. t pw1 t pw0 n n + 1 n + 2 n + 3 n + 4 n 3n 2n 1 n n + 1 td = 13ns clock 2v analog input data output 2v : analog signal sampling point tr = 4.5ns tf = 4.5ns 2.5v t plz t phz 10% 90% t pzh 1.3v 1.3v t pzl 10% 90% oe input output 1 5v 0v v oh v ol ( dv ss ) v oh ( dv dd ) v ol output 2 input signal voltage step digital output code msb lsb v rt : : : : v rb 0 : 127 128 : 255 1 1 1 1 1 1 1 1 : 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 : 0 0 0 0 0 0 0 0 timing chart i . timing chart ii .
7 CXD1179Q electrical characteristics analog characteristics (fc = 35msps, v dd = 5 v, v rb = 0.5 v, v rt = 2.5 v, ta = 25 c) conversion speed analog input band width ( 1 db) offset voltage ? 1 integral non-linearity error differential non-linearity erro r differential gain error differential phase error aperture jitter sampling delay clamp offset voltage ? 2 clamp pulse delay fc bw e ot e ob e l e d dg dp t aj t sd eoc t cpd 0.5 60 +55 20 30 v dd = 4.75 to 5.25 v ta = 40 to +85 c v in = 0.5 to 2.5 v f in = 1 khz ramp envelope potential difference to v rt potential difference to v rb end point ntsc 40 ire mod ramp fc = 14.3msps v in = dc, pws = 3 s 25 40 +75 +0.5 0.3 1 0.5 30 2 0 10 25 35 20 +95 +1.3 1.0 0.5 +20 +10 msps mhz mv lsb % deg ps ns mv ns item symbol conditions min. typ. max. unit v ref = 0.5 v v ref = 2.5 v ? 1 the offset voltage eob is a potential difference between v rb and a point of position where the voltage drops equivalent to 1/2 lsb of the voltage when the output data changes from 00000000 to 00000001 . eot is a potential difference between v rt and a potential of point where the voltage rises equivalent to 1/2lsb of the voltage when the output data changes from 11111111 to 11111110 . ? 2 clamp offset voltage varies individually. when using with r, g, b 3 channels, color sliding may be generated.
8 CXD1179Q dc characteristics (fc = 35msps, v dd = 5 v, v rb = 0.5 v, v rt = 2.5 v, ta = 25 c) supply current reference pin current analog input capacitance reference resistance (v rt to v rb ) self-bias i self-bias ii digital input voltage digital input current digital output current i dd i ref c in r ref v rb1 v rt1 v rb1 v rt2 v ih v il i ih i il i oh i ol i ozh i ozl 4.5 230 0.52 1.96 2.13 3.5 1.1 3.7 fc = 35msps ntsc ramp wave input v in = 1.5 v + 0.07 vrms shorts vrb and vrbs shorts vrt and vrts vrb = agnd shorts vrt and vrts v dd = 4.75 to 5.25 v ta = 40 to +85 c v dd = max oe = v ss v dd = min oe = v dd v dd = max 16 6.1 8 330 0.56 2.10 2.33 2.5 6.5 22 8.7 440 0.60 2.24 2.53 0.5 5 5 16 16 ma ma pf ? v v v a ma a item symbol conditions min. typ. max. unit timing (fc = 35msps, v dd = 5 v, v rb = 0.5 v, v rt = 2.5 v, ta = 25 c) output data delay tri-state output enable time tri-state output disable time clamp pulse width ? 1 t dl t pzh t pzl t phz t plz t cpw 7 5 4 1.75 with ttl 1 gate and 10 pf load v dd = 4.75 to 5.25 v ta = 40 to +85 c r l = 1 k ? , c l = 15 pf oe = 5 v 0 v v dd = 4.75 to 5.25 v ta = 40 to +85 c r l = 1 k ? , c l = 15 pf oe = 0v 5 v v dd = 4.75 to 5.25 v ta = 40 to +85 c fc = 14msps, c in = 10 f for ntsc wave 13 8 6.5 2.75 18 14 11 3.75 ns ns ns s item symbol conditions min. typ. max. unit v ih = v dd v il = 0 v v oh = v dd 0.5 v v ol = 0.4 v v oh = v dd v ol = 0 v ? 1 the clamp pulse width is for ntsc as an example. adjust the rate to the clamp pulse cycle (1/15.75 khz for ntsc) for other processing systems to equal the values for ntsc.
9 CXD1179Q electrical characteristics measurement circuit integral non-linearity error differential non-linearity error } measurement circuit offset voltage +v v a < b a > b comparator a8 to a1 a0 b8 to b1 b0 dut CXD1179Q buffer s1 s2 8 8 controller dvm 8 clk (35mhz) v in 0 1 s1: on if a < b s2: on if b > a 000 00 to 111 10 maximum operational speed differential gain error } measurement circuit differential phase error s.g. ntsc signal source s.g. (cw) cxd 1179q 10bit d/a vector scope counter h.p.f ttl ecl amp ttl ecl fc 1 2 v in 8 8 620 5.2v clk 620 5.2v 1 2 cx20202a-1 error rate d.g d.p. 40 ire modulation 100 0 40 sync 0.5v 2.5v iae burst 2.5v 0.5v fc 1khz digital output current measurement circuit v dd v rt v in v rb clk oe gnd 2.5v 0.5v v oh + i oh v dd v rt v in v rb clk oe gnd v ol + i ol 2.5v 0.5v c l dv dd r l r l measurement point to output pin tri-state output measurement circuit note) c l includes capacitance of the probe and others.
10 CXD1179Q s (1) c (1) s (2) c (2) s (3) c (3) s (4) c (4) md (0) md (1) md (2) md (3) rv (0) rv (1) rv (2) rv (3) s (1) c (1) s (3) c (3) h (3) h (1) ld ( 1) ld (1) c (0) s (2) c (2) s (4) h (0) h (2) h (4) ld ( 2) ld (0) ld (2) out ( 2) out ( 1) out (0) out (1) vi (1) vi (2) vi (3) vi (4) analog input external clock upper comparators block upper data lower reference voltage lower comparators a block lower data a lower comparators b block lower data b digital output timing chart 3 operation (see block diagram and timing chart 3) 1. the CXD1179Q is a 2-step parallel system a/d converter featuring a 4-bit upper comparators group and 2 lower comparators groups of 4-bit each. the reference voltage that is equal to the voltage between vrt vrb/16 is constantly applied to the upper 4-bit comparator block. voltage that corresponded to the upper data is fed through the reference supply to the lower data. vrts and vrbs pins serve for the self generation of vrt (reference voltage top) and vrb (reference voltage bottom).
11 CXD1179Q 2. this ic uses an offset cancel type comparator and the comparator operates synchronously with an external clock. these modes are respectively indicated on the timing chart with s, h, c symbols. that is, the comparator performs input sampling (auto zero) mode, input hold mode and comparison mode using the external clock. 3. the operation of respective parts is as indicated in the chart. for instance input voltage vi (1) is sampled with the falling edge of the first clock by means of the upper comparator block and the lower comparator a block. the upper comparators block finalizes comparison data md (1) with the rising edge of the first clock. simultaneously the reference supply generates the lower reference voltage rv (1) that corresponded to the upper results. the lower comparator block finalizes comparison data ld (1) with the rising edge of the second clock. md (1) and ld (1) are combined and output as out (1) with the rising edge of the 3rd clock. accordingly there is a 2.5 clock delay from the analog input sampling point to the digital data output. operation notes 1. power supply and ground to reduce noise effects, separate the analog and digital systems close to the device. for both the digital and analog power supply pins, use a ceramic capacitor of about 0.1 f set as close as possible to the pin to bypass to the respective grounds. 2. analog input compared with the flash type a/d converter, the input capacitance of the analog input is rather small. however it is necessary to conduct the drive with an amplifier featuring sufficient band and drive capability. when driving with an amplifier of low output impedance, parasite oscillation may occur. that may be prevented by inserting a resistance of about 100 ? in series between the amplifier output and a/d input. 3. clock input the clock line wiring should be as short as possible also, to avoid any interference with other signals, separate it from other circuits. 4. reference input voltage between v rt to v rb is compatible with the dynamic range of the analog input. bypassing vrt and vrb pins to analog ground, by means of a capacitor about 0.1 f, the stable characteristics of the reference voltage are obtained. by shorting vrt and vrts, vrb and vrbs, the self-bias function that generates v rt = about 2.6 v and v rb = about 0.6 v, is activated. 5. timing analog input is sampled with the falling edge of clk and output as digital data with a delay of 2.5 clocks and with the following rising edge. the delay from the clock rising edge to the data output is about 13ns. 6. oe pin by connecting oe to dv ss output mode is obtained. by connecting oe to dv dd high impedance is obtained.
12 CXD1179Q application circuit (1) when clamp is used (self bias used) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 32 1 0.1 open latch ck q ? 0.01 clamp pulse in clock in aco4 +5v (analog) video in 75 ? 10 0.1 10p +5v (analog) 0.01 vref 20k gnd (analog) 29 30 31 0.01 gnd (digital) +5v (digital) d7 d6 d5 d4 d3 d2 d1 d0 ? the clamp pulse is latched by the sampling clock of adc, but that is not necessary for basic clamp operation. however, slight small beat may be generated as vertical sag according to the relationship between the sampling frequency and the clamp pulse frequency. at such time, the latch circuit is effective in this case.
13 CXD1179Q (2) digital clamp (self bias used) 2 3 4 5 6 7 8 9 10 11 12 13 16 17 18 19 20 21 22 23 24 25 26 27 28 32 1 0.1 open 0.01 clock in aco4 +5v (analog) video in 75 ? 10 0.1 10p 0.01 gnd (analog) 29 30 31 gnd (digital) dac, pwm, etc. latch, subtracter, comparator, etc. 14 15 clamp pulse in +5v (digital) clamp level setting data (3) when clamp is not used (self bias used) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 32 1 open 0.01 clock in aco4 +5v (analog) video in 75 ? 0.1 10p 0.01 gnd (analog) 29 30 31 gnd (digital) +5v (digital) +5v (digital) 0.1 d7 d6 d5 d4 d3 d2 d1 d0
sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin solder plating 42 / copper alloy 32pin qfp (plastic) 9.0 0.2 7.0 0.1 1.5 0.15 (8.0) 0.1 0.1 + 0.2 + 0.35 + 0.3 0.50 0 ? to 10 ? 0.8 b 1 8 9 32 16 17 24 25 m 0.24 0.2g qfp-32p-l01 p-qfp32-7x7-0.8 0.1 b = 0.30 0.10 ( 0.30) (0.127) + 0.15 detail a : solder a 0.127 0.05 + 0.10 package outline unit : mm CXD1179Q 14
15 CXD1179Q sony corporation sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin palladium plating copper alloy 32pin qfp (plastic) 9.0 0.2 7.0 0.1 1.5 0.15 (8.0) 0.1 0.1 + 0.2 + 0.35 + 0.3 0.50 0 ? to 10 ? 0.8 b 1 8 9 32 16 17 24 25 m 0.24 0.2g qfp-32p-l01 p-qfp32-7x7-0.8 0.1 b = 0.30 0.03 0.125 0.04 detail a : palladium a package outline unit : mm

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